NARA 5SDH-2
NARA 5SDH-2
It uses ProcLPscript() to parse the script file and build an AccelNET I/O list using IOTRANS and IODATA structures. The scripting language allows the list processor program to be changed without recompiling listp_v2(8) .
If F is between 16 and 23 the data field must be present and is used for the data to be written to CAMAC during this operation. Otherwise the data field is not required.
Data from a read operation imbedded here is not retrievable from the lprg script. However, it could be retrieved by the program using the script.
If F 0-7 data is read from CAMAC and placed in the memory location pointed to by the read data pointer and the read pointer is incremented.
If F 16-23 data is written to CAMAC from the memory location pointed to by the write data pointer and the write pointer is incremented.
Other F values do not use data.
If the Q=0 nothing is written or read and the appropriate data pointer is not incremented.
If F 0-7 data is read from CAMAC and placed in the memory location pointed to by the read data pointer and the read pointer is incremented.
If F 16-23 data is written to CAMAC from the memory location pointed to by the write data pointer and the write pointer is incremented.
Other F values do not use data.
The appropriate data pointer is always incremented.
This instruction is not written into the list processor instruction memory. If it is desired to include this instruction in the list processor program then use nrm or noq to build the correct CAMAC command in the list processor program.
This instruction is not written into the list processor instruction memory. If it is desired to include this instruction in the list processor program then use nrm or noq to build the correct CAMAC command in the list processor program.
This instruction is not written into the list processor instruction memory. If it is desired to include this instruction in the list processor program then use nrm or noq to build the correct CAMAC command in the list processor program.
This instruction is not written into the list processor instruction memory. If it is desired to include this instruction in the list processor program then use nrm or noq to build the correct CAMAC command in the list processor program.
This instruction is not written into the list processor instruction memory. If it is desired to include this instruction in the list processor program then use nrm or noq to build the correct CAMAC command in the list processor program.
The Phillips ADC is located in slot 5.
A KSC3610 counter module is located in slot 4. Two counter channels are used. One channel is connected to the sequencer electronics count signal. It increments each time the Sequence Controller completes one jumping cycle. This count is read and placed in the 1st word of the data block.
Five ADC channels ohannels are read and placed in list processer memory, then the ADC is reset.
The data block is six 24 bit words long and looks like this:
cycle_number adc0 adc1 adc2 adc3 adc4 adc5
This information will be uploaded into the computer by listp_v2(8) when told to do so by MBSseqTask(8) . After the data has been uploaded it is processed for output into logging files, online transmission and histogramming display.
The rules for processing the data blocks and an example script for processing the data created by this script may be found in pconv_v2(5) .
#
# list processer program for use with Phillips 7164
#
#
# setup
crate 4 # set the crate number
lpslot 22 # set the list processor slot number
# definition operations
define Nadc 5 # adc
define Ncntr 4 # counter
# initialization
reset # reset the list processor
book # book it
# set up list processer registers
IPw 0 # initialize instruction pointer
# RDw 0xfc0000 # initialize read data pointer
# this is done by listp program so don’t do it..
# set up jump table
stop # 0 trigger 1
stop # 1 trigger 2
stop # 2 trigger 3
stop # 3 trigger 4
stop # 4 trigger 5
stop # 5 trigger 6
jump unc 7 # 6 trigger 7
# trigger 7 list
nrm Ncntr 0 0 # 7 read counter
nrm Nadc 0 0 # 8 read adc chan 0
nrm Nadc 1 0 # 9 read adc chan 1
nrm Nadc 2 0 # 10 read adc chan 2
nrm Nadc 3 0 # 11 read adc chan 3
nrm Nadc 4 0 # 12 read adc chan 4
nrm Nadc 1 11 # 12 clear the adc hit register and lam
jump trg 0 # 13 jump back to beginning and await trigger
IPw 0 # reset instruction pointer to beginning
# enable # fire up list processor
# don’t do this (lp will be enabled by program)
