Table of Contents

Name

nec_gateII - NEC Gate Generator Mark II CAMAC module

Description

CAMAC Register Layout

See the section Register Bit Layout of details about each register.

A0 F16 - State Register 0
A1 F16 - State Register 1
A2 F16 - State Register 2
A3 F16 - State Register 3
A4 F16 - State Register 4
A5 F16 - State Register 5
A6 F16 - State Register 6
A7 F16 - State Register 7
A8 F16 - State Register 8
A9 F16 - State Register 9
A10 F16 - State Register 10
A11 F16 - State Register 11
A12 F16 - State Register 12
A13 F16 - State Register 13
A14 F16 - State Register 14
A15 F16 - State Register 15

A0 F17 - Control Status Register

This register is only implemented in the MarkIII design.

Register Bit Layout

Control/Status Register
This is an 8 bit register whose bits assignments are:

bits 3-0 - marker output select
bit 4 - gate15 - select gate/clock
bit 5 - gate16 - select gate/CntActOut

State Registers
There is one register for each possible state. One bit in each state register is used to determine if the gate associated with that bit is on or off during the state.

Bit 0 corresponds to gate 1 etc.

Applicable part numbers

2HA054210 - Gate Generator
This is the 1st wirewrapped version of the circuit.

It has 8 gate outputs, a count active output, and an analog marker output which uses 2 different pulse heights to show the state change.

Each gate, the CAO, and the marker have a 2 pin Lemo connector.

2HA054630 - Gate Generator MarkII
This is the 2nd wirewrapped version of the circuit.

It has 16 gate outputs, a count active output, and an analog marker output which uses 2 different pulse heights to show the state change.

The gate outputs are in groups of 4 on a female D9 connector.

The marker output is a 2 pin Lemo connector.

2HA0????0 - Gate Generator MarkIII
This is an FPGA based circuit design.

It has 16 gate outputs and another output which can be programmatically assigned to any of the gate outputs.

Gate15 may be switched between the system clock and the gate signal.

Gate16 may be switched between the count active signal clock and the gate signal.

The gate outputs are in groups of 4 on a female D9 connector.

The marker output is a 2 pin Lemo connector. It is a differentially driven TTL signal of the same type as the gate signals.

Software support

Support for this module in AccelNET is provided by MBSgateTask. See the manual page MBSgateTask(8) for more information.

Manual page revision

$Id: nec_gate.6,v 1.2 2006/10/02 17:33:33 kitchen Exp $

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